Conventional semiconductor devices generally include a semiconductor substrate, usually a silicon substrate, and a plurality of sequentially formed dielectric interlayers such as silicon dioxide and conductive paths or interconnects made of conductive materials. Copper and copper alloys have recently received considerable attention as interconnect materials because of their superior electromigration and low resistivity characteristics. Interconnects are usually formed by filling copper in features or cavities etched into the dielectric interlayers by a metallization process. The preferred method of copper metallization process is electroplating. In an integrated circuit, multiple levels of interconnect networks laterally extend with respect to the substrate surface. Interconnects formed in sequential layers can be electrically connected using vias or contacts. In a typical process, first an insulating layer is formed on the semiconductor substrate. Patterning and etching processes are performed to form features such as trenches and vias in the insulating layer. After coating features on the surface with a barrier and then a seed layer, copper is electroplated to fill the features. However, the plating process, in addition to the filling the features, also results in a copper layer on the top surface of the substrate. This excess copper is called overburden and it should be removed before the subsequent process steps.
FIG. 1A shows an exemplary portion 8 of such plated substrate 9, for example a silicon wafer. It should be noted that the substrate 9 may include devices or other metallic and semiconductor sections, which are not shown in FIG. 1A for the purpose of clarification. As shown in FIG. 1A, features such as a via 10, and a trench 13 are formed in an insulation layer 14, such as a silicon dioxide layer, that is formed on the substrate 9. The via and the trench 13 as well as top surface 15 of the insulation layer 14 are covered and filled with a deposited copper layer 16 through an electroplating process. Conventionally, after patterning and etching, the insulation layer 14 is first coated with a barrier layer 18, typically, a Ta or Ta/TaN composite layer. The barrier layer 18 coats the via and the trench as well as the surface 15 of the insulation layer to ensure good adhesion and acts as a barrier material to prevent diffusion of the copper into the semiconductor devices and into the insulation layer. Next a seed layer (not shown), which is often a copper layer, is deposited on the barrier layer. The seed layer forms a conductive material base for copper film growth during the subsequent copper deposition. As the copper film is electroplated, the deposited copper layer 16 quickly fills the via 10 but coats the wide trench 13 and the top surface 15 in a conformal manner. When the deposition process is continued to ensure that the trench is also filled, a copper layer or overburden is formed on the substrate 9. Conventionally, after the copper plating, various material removal processes, for example, chemical mechanical polishing (CMP), etching or electroetching, can be used to remove the unwanted overburden layer.
The CMP process conventionally involves pressing a semiconductor wafer or other such substrate against a moving polishing surface that is wetted with a polishing slurry. The slurries may be basic, neutral or acidic and generally contain alumina, ceria, silica or other hard abrasive ceramic particles. The polishing surface is typically a planar pad made of polymeric materials well known in the art of CMP. Some polishing pads contain abrasive particles (fixed abrasive pads). These pads may be used in conjunction with CMP solutions that may not contain any abrasive particles. The polishing slurry or solution may be delivered to the surface of the pad or may be flowed through the pad to its surface if the pad is porous. During a CMP process a wafer carrier holds a wafer to be processed and places the wafer surface on a CMP pad and presses the wafer against the pad with controlled pressure while the pad is rotated. The pad may also be configured as a linear polishing belt that can be moved laterally as a linear belt. The process is performed by moving the wafer against the pad, moving the pad against the wafer or both as polishing slurry is supplied to the interface between the pad and the wafer surface.
As shown in FIG. 1B, CMP is first applied to reduce the thickness of the copper layer down to the barrier layer 18 that covers the top surface 15 of the insulation layer 14. Subsequently, the barrier layer 18 on the top surface is removed to confine the copper and the remaining barrier in the vias 10, 12 and trench 13. However, during these processes, determining the polishing endpoint, whether the copper layer is polished down to the barrier layer or the barrier layer is polished down to the insulation layer, is one of the important problems in the industry.
U.S. Pat. No. 5,605,760 describes a polishing pad that is made of solid uniform polymer sheet. The polymer sheet is transparent to light at a specified wavelength range. The surface of the polymer sheet does not contain any abrasive material and does not have any intrinsic ability to absorb or transport slurry particles.
More recently, endpoint detection systems have been implemented with rotating pad or linear belt systems having a window or windows in them. In such cases as the pad or the belt moves, it passes over an in-situ monitor that takes reflectance measurements from the wafer surface. Changes in the reflection indicate the endpoint of the polishing process. However, windows opened in the polishing pad can complicate the polishing process and may disturb the homogeneity of the pad or the belt. Additionally, such windows may cause accumulation of polishing byproducts and slurry.
Therefore, a continuing need exists for a method and apparatus which accurately and effectively detects an endpoint on a substrate when the substrate is polished using the CMP processes.
As shown in FIG. 1B, CMP is first applied to reduce the thickness of the copper layer down to the barrier layer 18 that covers the top surface 15 of the insulation layer 14. Subsequently, the barrier layer 18 on the top surface is removed to confine the copper and the remaining barrier in the via 10 and trench 13. However, during these processes, uniform reduction of the thickness of the polished copper layer is one of the important problems in the industry. The thickness uniformity of the metal layer must be maintained while it is processed so that the overpolish after copper endpoint is minimized and the substrate is not over-polished, since overpolishing may cause excessive dishing, erosion and other defects. Further, underpolishing of the copper layer and barrier layers may cause electrical shorts or other defects. The non-uniformity during the polishing process may be due to either a non-uniform polishing process or a non-uniform thickness of the metal layers on the substrate or both.
Polishing of insulator layers of a substrate is another application of CMP. Shallow trench isolation (STI) is a process by which insulating trenches are formed in the surface of the substrate to prevent electromigration between neighboring circuits. The trenches are typically filled with silicon nitride (Si3N4) and silicon dioxide (SiO2). To fill the trenches, a layer of silicon nitride is first deposited on the surface of the substrate, followed by an overlying layer of silicon dioxide. Excess silicon dioxide and silicon nitride must be removed from the surface of the substrate, leaving a smooth layer of silicon nitride over most of the substrate surface and layers of silicon dioxide and silicon nitride filling the trench area. The removal of excess silicon dioxide and silicon nitride is typically performed by CMP.
FIG. 1C shows a cross-sectional view of an exemplary portion 51 of a substrate 52, for example a silicon wafer, that is covered with two layers of insulating material. A trench 53, suitable for STI, is formed in the surface of the substrate 52. A bottom insulating layer 54 and a top insulating layer 55 cover the surface of the substrate 52, including the trench 53. The composition of the bottom insulating layer 54 and the top insulating layer 55 may be, for example, silicon nitride and silicon dioxide respectively. Note that the insulating layers 54 and 55 cover the entire surface of the substrate 52. To complete the STI process, excess insulating material must be removed.
FIG. 1D shows a cross-sectional view of the exemplary portion 51 of the substrate 52 after the insulating layers 54 and 55 have been polished to a desired degree, i.e., after excess insulating material has been removed. The polishing of the insulating layers may be performed by, for example, CMP. Note that a smooth layer of the insulating layer 54, i.e. silicon nitride covers the surface of the substrate 52 and that the insulating layers 54 and 55 (i.e., silicon nitride and silicon dioxide) fill the trench 53.
Problems with current STI technology include a difficulty in performing silicon dioxide thickness measurement by optical interferometry because the thickness measurement signal repeats itself periodically with increasing or decreasing silicon dioxide thickness. Additionally, the thickness measurement signal is sensitive to environmental factors such as moisture (water film) and detect angle.
An additional problem with current technology is that conventional metrology tools require that a substrate be removed from its carrier head to perform endpoint detection.
A uniform polishing process will significantly reduce CMP cost while increasing process throughput. As the wafer sizes become larger, e.g., 300 mm and beyond, a planar reduction of thickness in a uniform manner becomes more difficult due to the larger surface area of the wafer.
Consequently, there is need for an improved method and apparatus for monitoring and maintaining the uniformity of the polished layer when the substrate is polished using CMP processes.